UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 346

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

346
(e) Normal reception
R
X
D6n (input)
INTSR6n
Reception is enabled and the R
interface operation mode register 6n (ASIM6n) is set to 1 and then bit 5 (RXE6n) of ASIM6n is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the R
detected. When the set value of baud rate generator control register 6n (BRGC6n) has been counted, the
R
recognized as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6n) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR6n) is generated and the data of RXS6n is written to receive buffer register 6n (RXB6n). If
an overrun error (OVE6n) occurs, however, the receive data is not written to RXB6n.
Even if a parity error (PE6n) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an error interrupt (INTSR6n/INTSRE6n) is generated on completion of reception.
Cautions 1. If a reception error occurs, read ASIS6n and then RXB6n to clear the error flag.
Remark n = 0, 1
X
RXB6n
D6n pins input is sampled again (
2. Reception is always performed with the “number of stop bits = 1”. The second stop
3. Be sure to read asynchronous serial interface reception error status register 6n
Otherwise, an overrun error will occur when the next data is received, and the
reception error status will persist.
bit is ignored.
(ASIS6n) before reading RXB6n.
Figure 14-27. Reception Completion Interrupt Request Timing
Start
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
D0
D1
X
D6n pins input is sampled when bit 7 (POWER6n) of asynchronous serial
User’s Manual U17554EJ4V0UD
D2
in Figure 14-27). If the R
D3
D4
D5
D6
X
D6n pins are low level at this time, it is
D7
Parity
Stop
X
D6n pins input is