UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 146

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

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(2) Example of setting procedure when using the external main system clock
(3) Example of setting procedure when using high-speed system clock as CPU clock and peripheral
<4> Waiting for the stabilization of the oscillation of X1 clock
Cautions 1. Do not change the value of EXCLK and OSCSEL while the X1 clock is operating.
<1> Setting frequency (OSCCTL register)
<2> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register)
<3> Controlling external main system clock input (MOC register)
Cautions 1. Do not change the value of EXCLK and OSCSEL while the external main system clock is
hardware clock
<1> Setting high-speed system clock oscillation
Check the OSTC register and wait for the necessary time.
During the wait time, other software processing can be executed with the internal high-speed oscillation
clock.
Using AMPH, set the frequency to be used.
Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can
Remark f
When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input
mode.
When MSTOP is cleared to 0, the input of the external main system clock is enabled.
(See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of <1> is not necessary when high-speed system clock is already operating.
AMPH
EXCLK
2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to
2. Set the external main system clock after the supply voltage has reached the operable
0
1
1
be changed only once after a reset release. The clock supply to the CPU is stopped for the
duration of 160 external clocks after AMPH is set to 1.
Note
be used (see CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) or
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)).
operating.
voltage of the clock to be used (see CHAPTER 27
((A) GRADE PRODUCTS) or CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE
PRODUCTS)).
XH
4 MHz ≤ f
10 MHz < f
: High-speed system clock oscillation frequency
OSCSEL
1
XH
XH
External clock input mode
≤ 10 MHz
Speed System Clock Pin
Operation Mode of High-
≤ 20 MHz
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17554EJ4V0UD
Operating Frequency Control
Note
I/O port
P121/X1 Pin
ELECTRICAL SPECIFICATIONS
External clock input
P122/X2/EXCLK Pin