UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 221

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(9) Capture operation
(10) Edge detection
(11) Timer operation
(a) When valid edge of TI00n is specified as count clock
(b) Pulse width to accurately capture value by signals input to TI01n and TI00n pins
(c) Generation of interrupt signal
(d) Note when CRC0n1 (bit 1 of capture/compare control register 0n (CRC0n)) is set to 1
(a) Specifying valid edge after reset
(b) Sampling clock for eliminating noise
The signal input to the TI00n/TI01n pin is not acknowledged while the timer is stopped, regardless of the
operation mode of the CPU.
Remarks 1. f
When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified
as a trigger does not operate correctly.
To accurately capture the count value, the pulse input to the TI00n and TI01n pins as a capture trigger must
be wider than two count clocks selected by PRM0n (see Figure 7-13).
The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM00n
and INTTM01n) are generated at the rising edge of the next count clock (see Figure 7-13).
When the count value of the TM0n register is captured to the CR00n register in the phase reverse to the
signal input to the TI00n pin, the interrupt signal (INTTM00n) is not generated after the count value is
captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not
performed but the INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n signal
when the external interrupt is not used.
If the operation of the 16-bit timer/event counter 0n is enabled after reset and while the TI00n or TI01n pin is
at high level and when the rising edge or both the edges are specified as the valid edge of the TI00n or TI01n
pin, then the high level of the TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n or
TI01n pin is pulled up. However, the rising edge is not detected when the operation is once stopped and
then enabled again.
The sampling clock for eliminating noise differs depending on whether the valid edge of TI00n is used as the
count clock or capture trigger. In the former case, the sampling clock is fixed to f
clock selected by PRM0n is used for sampling.
When the signal input to the TI00n pin is sampled and the valid level is detected two times in a row, the valid
edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 7-13).
2. n = 0 to 3
PRS
: Peripheral hardware clock frequency
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
User’s Manual U17554EJ4V0UD
PRS
. In the latter, the count
221