UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 152

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

6.6.4 Controlling internal low-speed oscillation clock
6.6.5 Clocks supplied to CPU and peripheral hardware
of registers.
152
(1) To stop the internal low-speed oscillation clock (example of setting method)
(2) To oscillate the internal low-speed oscillation clock (example of setting method)
The internal low-speed oscillation clock is a clock for the watchdog timer. It cannot be used as the CPU clock.
With this clock, only the following peripheral hardware can operate.
• Watchdog timer
• 8-bit timer H1 (if f
In addition, the following operation modes can be selected by the option byte.
• Internal low-speed oscillation clock oscillation cannot be stopped
• Internal low-speed oscillation clock oscillation can be stopped by software
After a reset release, the internal low-speed oscillation clock automatically oscillates.
The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting
Remarks 1. XSEL:
Caution If “internal low-speed oscillation clock oscillation cannot be stopped” is selected by the option
<1> Setting LSRSTOP to 1 (RCM register)
<1> Clearing LSRSTOP to 0 (RCM register)
XSEL
0
0
1
1
1
1
1
1
1
1
If LSRSTOP is set to 1, the internal low-speed oscillator oscillation is stopped.
If LSRSTOP is cleared to 0, the internal low-speed oscillation clock is oscillated.
2. CSS:
3. MCM0: Bit 0 of MCM
4. EXCLK: Bit 7 of the clock operation mode select register (OSCCTL)
byte, oscillation of the internal low-speed oscillation clock cannot be controlled.
Table 6-3. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting
CSS
0
1
0
0
0
0
1
1
1
1
RL
is selected as the count clock)
Bit 2 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
MCM0
×
×
0
0
1
1
0
0
1
1
CHAPTER 6 CLOCK GENERATOR
EXCLK
×
×
0
1
0
1
0
1
0
1
User’s Manual U17554EJ4V0UD
Internal high-speed oscillation clock
Subsystem clock
Internal high-speed oscillation
clock
X1 clock
External main system clock
Subsystem clock
Clock Supplied to CPU
Supplied Clock
Internal high-speed oscillation
clock
X1 clock
External main system clock
X1 clock
External main system clock
X1 clock
External main system clock
Clock Supplied to Peripheral
Hardware