UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 530

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

17.4 Interrupt Servicing Operations
17.4.1 Maskable interrupt acknowledgement
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1).
acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from
generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 17-4 below.
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into
the PC and branched.
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A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
For the interrupt request acknowledgement timing, see Figures 17-8 and 17-9.
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 17-7 shows the interrupt request acknowledgement algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
Restoring from an interrupt is possible by using the RETI instruction.
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/f
Table 17-4. Time from Generation of Maskable Interrupt Until Servicing
When ××PR = 0
When ××PR = 1
CPU
(f
CPU
: CPU clock)
CHAPTER 17 INTERRUPT FUNCTIONS
User’s Manual U17554EJ4V0UD
7 clocks
8 clocks
Minimum Time
However, a low-priority interrupt request is not
32 clocks
33 clocks
Maximum Time
Note