UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 322

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

322
Address: FF2FH After reset: 00H R
ASIS61
Cautions 1.
Symbol
Figure 14-10. Format of Asynchronous Serial Interface Reception Error Status Register 61 (ASIS61)
2.
3.
4.
OVE61
PE61
FE61
The operation of the PE61 bit differs depending on the set values of the PS611 and PS601
bits of asynchronous serial interface operation mode register 61 (ASIM61).
The first bit of the receive data is checked as the stop bit, regardless of the number of stop
bits.
If an overrun error occurs, the next receive data is not written to receive buffer register 61
(RXB61) but discarded.
If data is read from ASIS61, a wait cycle is generated. Do not read data from ASIS6 when the
CPU is operating on the subsystem clock and the high-speed system clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
7
0
0
1
0
1
0
1
If POWER61 = 0 and RXE61 = 0, or if ASIS61 register is read
If the parity of transmit data does not match the parity bit on completion of reception
If POWER61 = 0 and RXE61 = 0, or if ASIS61 register is read
If the stop bit is not detected on completion of reception
If POWER61 = 0 and RXE61 = 0, or if ASIS61 register is read
If receive data is set to the RXB61 register and the next reception operation is completed before the
data is read.
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
6
0
5
0
User’s Manual U17554EJ4V0UD
Status flag indicating framing error
Status flag indicating overrun error
Status flag indicating parity error
4
0
3
0
PE61
2
FE61
1
OVE61
0