UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 157

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(9) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
(B) → (E)
(C) → (F)
(D) → (G)
Status Transition
(D) → (B)
(B) → (H)
(C) → (I)
Remarks 1. (A) to (I) in Table 6-4 correspond to (A) to (I) in Figure 6-14.
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
2. MCM0:
(Setting sequence of SFR registers)
Status Transition
Status Transition
CSS:
RSTS, RSTOP: Bits 7 and 0 of the internal oscillator mode register (RCM)
Table 6-4. CPU Clock Transition and SFR Register Setting Examples (4/4)
Setting Flag of SFR Register
(Setting sequence)
Bit 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17554EJ4V0UD
Unnecessary if the CPU is operating with
the internal high-speed oscillation clock
Executing HALT instruction
Stopping peripheral functions that
cannot operate in STOP mode
RSTOP
0
Confirm this flag
RSTS
is 1.
Setting
Setting
Executing STOP instruction
Unnecessary if
XSEL is 0
MCM0
0
↑
CSS
0
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