UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 398

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

398
REPS, REC[6:0]
in C0ERC
register
OPMODE[2:0]
in C0CTRL
register
(user readings)
OPMODE[2:0]
in C0CTRL
register
(user writings)
TEC[7:0]
in C0ERC
register
BOFF bit
in C0INFO
register
(6) Initializing CAN module error counter register (C0ERC) in initialization mode
(b) Forced recovery operation that skips bus-off recovery sequence
If it is necessary to initialize the CAN module error counter register (C0ERC) and CAN module information
register (C0INFO) for debugging or evaluating a program, they can be initialized to the default value by
setting the CCERC bit of the C0CTRL register in the initialization mode.
completed, the CCERC bit is automatically cleared to 0.
Cautions 1. This function is enabled only in the initialization mode. Even if the CCERC bit is set to
Figure 16-17. Recovery Operation from Bus-off State through Normal Recovery Sequence
80H
»error-passive«
The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping
the bus-off recovery sequence. Here is the procedure.
First, the CAN module requests to enter the initialization mode. For the operation and points to be noted
at this time, refer to (a) Recovery operation from bus-off state through normal recovery sequence.
Next, the module requests to enter an operation mode. At the same time, the CCERC bit of the C0CTRL
register must be set to 1.
As a result, the bus-off recovery sequence defined by the CAN protocol ISO 11898 is skipped, and the
module immediately enters the operation mode. In this case, the module is connected to the CAN bus
after it has monitored 11 consecutive recessive-level bits. For details, refer to the processing in Figure
16-56.
Caution This function is not defined by the CAN protocol ISO 11898. When using this function,
TEC[7:0]
2. The CCERC bit can be set at the same time as the request to enter a CAN operation
TEC > FFH
00H
1 in a CAN operation mode, the C0ERC and C0INFO registers are not initialized.
mode.
00H
thoroughly evaluate its effect on the network system.
80H
FFH
REPS, REC[6:0]
FFH < TEC [7:0]
»bus-off«
<1>
CHAPTER 16 CAN CONTROLLER
FFH
00H
User’s Manual U17554EJ4V0UD
<2>
»bus-off-recovery-sequence«
00H
Undefined
00H
00H
When initialization has been
<3>
00H
00H
»error-active«
00H
TEC[7:0]
REPS, REC[6:0]
80H
80H