UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 133

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(5) Clock operation mode select register (OSCCTL)
This register selects the operation modes of the high-speed system and subsystem clocks.
OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FFEFH
OSCCTL
Symbol
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
EXCLKS
EXCLK
EXCLK
AMPH
Figure 6-6. Format of Clock Operation Mode Select Register (OSCCTL)
<7>
0
0
1
1
0
0
1
1
0
1
After reset: 00H
2. Set AMPH before setting the peripheral functions after a reset release. The value
3. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
4. AMPH can be changed only once after a reset release.
4 MHz ≤ f
10 MHz < f
OSCSELS
OSCSEL
OSCSEL
exceeds 10 MHz.
of AMPH can be changed only once after a reset release. When the high-speed
system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU
clock is stopped for 4.06 to 16.12
speed system clock (external clock input) is selected as the CPU clock, supply of
the CPU clock is stopped for the duration of 160 external clocks after AMPH is
set to 1.
stopped for 4.06 to 16.12
high-speed oscillation clock is selected as the CPU clock, or for the duration of
160 external clocks when the high-speed system clock (external clock input) is
selected as the CPU clock. When the high-speed system clock (X1 oscillation) is
selected as the CPU clock, the oscillation stabilization time is counted after the
STOP mode is released.
<6>
0
1
0
1
0
1
0
1
XH
XH
≤ 10 MHz
R/W
CHAPTER 6 CLOCK GENERATOR
I/O port mode
X1 oscillation mode
I/O port mode
External clock input
mode
I/O port mode
XT1 oscillation mode
I/O port mode
External clock input
mode
≤ 20 MHz
EXCLKS
clock operation mode
High-speed system
<5>
Subsystem clock
User’s Manual U17554EJ4V0UD
operation mode
OSCSELS
<4>
Operating frequency control
μ
s after the STOP mode is released when the internal
I/O port
Crystal/ceramic resonator connection
I/O port
I/O port
I/O port
Crystal resonator connection
I/O port
I/O port
μ
3
0
P123/XT1 pin
s after AMPH is set to 1. When the high-
P121/X1 pin
2
0
External clock input
External clock input
P124/XT2/EXCLKS pin
P122/X2/EXCLK pin
1
0
AMPH
<0>
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