UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 429

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Remark - The TSTAT bit is set to 1 under the following conditions (timing).
Remarks 1.
Remark The AL bit is valid only in the single-shot mode.
Remarks 1. Detection of a valid receive message frame is not dependent upon storage in the
CCERC
TSTAT
VALID
AL
0
1
0
1
0
1
0
1
- The TSTAT bit is cleared to 0 under the following conditions (timing).
- The SOF bit of a transmit frame is detected
- The first bit of an error flag is detected during a transmit frame
- During transition to bus-off state
- On occurrence of arbitration loss in transmit frame
- On detection of recessive level at the second bit of the interframe space
- On transition to the initialization mode at the first bit of the interframe space
2.
3.
4.
2.
3.
4.
Transmission is stopped.
Transmission is in progress.
The C0ERC and C0INFO registers are not cleared in the initialization mode.
The C0ERC and C0INFO registers are cleared in the initialization mode.
Re-transmission is not executed in case of an arbitration loss in the single-shot mode.
Re-transmission is executed in case of an arbitration loss in the single-shot mode.
A valid message frame has not been received since the VALID bit was last cleared to 0.
A valid message frame has been received since the VALID bit was last cleared to 0.
receive message buffer (data frame) or transmit message buffer (remote frame).
The CCERC bit is used to clear the C0ERC and C0INFO registers for re-initialization or
forced recovery from the bus-off state. This bit can be set to 1 only in the
initialization mode.
When the C0ERC and C0INFO registers have been cleared, the CCERC bit is also
cleared to 0 automatically.
The CCERC bit can be set to 1 at the same time as a request to change the
initialization mode to an operation mode is made.4. The CCERC bit is read-only in the
CAN sleep mode or CAN stop mode.
The receive data may be corrupted in case of setting the CCERC bit to (1)
immediately after entering the INIT mode from self-test mode.
Clear the VALID bit (0) before changing the initialization mode to an operation mode.
If only two CAN nodes are connected to the CAN bus with one transmitting a
message frame in the normal operation mode and the other in the receive-only
mode, the VALID bit is not set to 1 before the transmitting node enters the error
passive state, because in receive-only mode no acknowledge is generated.
In order to clear the VALID bit, set the Clear VALID bit to 1 first and confirm that the
VALID bit is cleared. If it is not cleared, perform clearing processing again.
Bit to Set Operation in Case of Arbitration Loss
CHAPTER 16 CAN CONTROLLER
Valid Receive Message Frame Detection Bit
User’s Manual U17554EJ4V0UD
Transmission Status Bit
Error Counter Clear Bit
429