UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 144

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Subsystem clock (f
144
(when XT1 oscillation
oscillation clock (f
Internal reset signal
(when X1 oscillation
Internal high-speed
Note Check the oscillation stable time of X1 clock with an oscillation stable time counter status register (OSTC)
Cautions 1. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
system clock (f
<1> The internal reset signal by the power-on clear (POC) circuit is generated after a power supply injection.
<2> If power supply voltage exceeds 1.59 V (TYP.), reset will be canceled and the oscillation start of the high-
<3> After reset release, after reset processing is performed, CPU carries out a start of operation with high-speed
<4> X1 clock or XT1 clock should set up an oscillation start by software (see (1) in 6.6.1 Controlling high-
<5> When you change CPU to X1 clock or XT1 clock, set up a change by software after the oscillation stability
Power supply
voltage (V
High-speed
CPU clock
speed oscillator will be carried out automatically.
oscillation clock.
speed system clock and (1) in 6.6.3 Example of controlling subsystem clock).
waiting of a clock (see (3) in 6.6.1 Controlling high-speed system clock and (3) in 6.6.3 Example of
controlling subsystem clock).
selected)
selected)
when STOP mode release in case the time of reset release (figure 6-13) and a CPU clock are high-speed
oscillation clocks . Moreover, when a CPU clock is a high-speed system clock (X1 oscillation), set up the
oscillation stable time at the time of STOP mode release by the oscillation stable time selection register
(OSTS).
Figure 6-13 Operation of the clock generating circuit when power supply voltage injection
DD
SUB
0 V
RH
XH
2. It is not necessary to wait for the oscillation stabilization time when an external clock input
)
)
)
)
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
from the EXCLK and EXCLKS pins is used.
<1>
(When 2.7 V/1.59V POC mode setup (option byte: LVISTART = 1))
Waiting for oscillation accuracy
stabilization (86 to 361 s)
2.7 V (TYP.)
CHAPTER 6 CLOCK GENERATOR
Starting X1 oscillation
is set by software.
User’s Manual U17554EJ4V0UD
<3>
<2>
Starting XT1 oscillation
is set by software.
Reset processing
<4>
(11 to 45 s)
oscillation stabilization time:
Internal high-speed
oscillation clock
2
<4>
11
/f
X1 clock
X
to 2
16
/f
X
Note
<5>
High-speed system clock
Switched by
software
<5>
Subsystem clock