MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 101

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

3.1.2
The MAC unit supports the ColdFire integer multiply instructions (MULS and MULU) and provides
additional functionality for multiply-accumulate operations. The added MAC instructions to the ColdFire
ISA provide for the multiplication of two numbers, followed by the addition or subtraction of this number
to or from the value contained in the accumulator. The product may be optionally shifted left or right one
bit before the addition or subtraction takes place. Hardware support for saturation arithmetic may be
enabled to minimize software overhead when dealing with potential overflow conditions using signed or
unsigned operands.
These MAC operations treat the operands as one of the following formats:
To maintain compactness, the MAC module is optimized for 16-bit multiplications. Two 16-bit operands
produce a 32-bit product. Longword operations are performed by reusing the 16-bit multiplier array at the
expense of a small amount of extra control logic. Again, the product of two 32-bit operands is a 32-bit
result. For longword integer operations, only the least significant 32 bits of the product are calculated. For
fractional operations, the entire 63-bit product is calculated and then either truncated or rounded to a 32-bit
result using the round-to-nearest (even) method.
Because the multiplier array is implemented in a 3-stage pipeline, MAC instructions can have an effective
issue rate of one clock for word operations, three for longword integer operations, and four for 32-bit
fractional operations. Arithmetic operations use register-based input operands, and summed values are
stored internally in the accumulator. Thus, an additional MOVE instruction is necessary to store data in a
general-purpose register. MAC instructions can choose the upper or lower word of a register as the input,
which helps filtering operations in which one data register is loaded with input data and another is loaded
with coefficient data. Two 16-bit MAC operations can be performed without fetching additional operands
between instructions by alternating the word choice during the calculations.
The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can
be moved efficiently by using the MOVEM instruction, which automatically generates line-sized burst
references and is ideal for filling registers quickly with input data, filter coefficients, and output data.
Loading an operand from memory into a register during a MAC operation makes some DSP operations,
especially filtering and convolution, more manageable.
The MACSR has a 4-bit operational mode field and three condition flags. The operational mode bits
control the overflow/saturation mode, whether operands are signed or unsigned, whether operands are
treated as integers or fractions, and how rounding is performed. Negative, zero, and overflow flags are also
provided.
The three program-visible MAC registers, a 32-bit accumulator (ACC), the MAC mask register (MASK),
and MACSR, are described in
Freescale Semiconductor
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Signed integers
Unsigned integers
Signed, fixed-point, fractional numbers
General Operation
MCF5272 ColdFire
Section 3.1.1, “MAC Programming
®
Integrated Microprocessor User’s Manual, Rev. 3
Model.”
Hardware Multiply/Accumulate (MAC) Unit
3-3