MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 384

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

UART Modules
16.5.2.2
The receiver is enabled through its UCRn, as described in
(UCRn).”
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on RxD, the state of RxD
is sampled each 16× clock for eight clocks, starting one-half clock after the transition (asynchronous
operation) or at the next rising edge of the bit time clock (synchronous operation). If RxD is sampled high,
the start bit is invalid and the search for the valid start bit begins again.
If RxD is still low, a valid start bit is assumed and the receiver continues sampling the input at one-bit time
intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is
assembled and one stop bit is detected. Data on the RxD input is sampled on the rising edge of the
programmed clock source. The lsb is received first. The data is then transferred to a receiver holding
register and USRn[RxRDY] is set. If the character is less than eight bits, the most significant unused bits
in the receiver holding register are cleared.
After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a non-zero
character is received without a stop bit (framing error) and RxD remains low for one-half of the bit period
after the stop bit is sampled, the receiver operates as if a new start bit were detected. Parity error, framing
error, overrun error, and received break conditions set the respective PE, FE, OE, RB error, and break flags
in the USRn at the received character boundary and are valid only if USRn[RxRDY] is set.
If a break condition is detected (RxD is low for the entire character including the stop bit), a character of
all zeros is loaded into the receiver holding register (RHR) and USRn[RB,RxRDY] are set. RxD must
return to a high condition for at least one-half bit time before a search for the next start bit begins.
16-24
USRn[RxRDY]
USRn[FFULL]
USRn[OE]
Receiver
Enabled
Overrun
internal
module
Figure 16-26
select
RTS
RxD
Receiver
4
UOP0[RTS] = 1
MCF5272 ColdFire
Manually asserted first time,
automatically negated if overrun occurs
C1
shows receiver functional timing.
Status
Data
(C1)
C2
Figure 16-26. Receiver Timing
®
Integrated Microprocessor User’s Manual, Rev. 3
C3
C25
Section 16.3.5, “UART Command Registers
is lost
C26
C26
Status
(C2)
Data
C27
C26, C27, and C82 are lost
Automatically asserted
when ready to receive
Status
(C3)
Data
Freescale Semiconductor
Status
(C4)
Data
C28
command
Reset by
C29