MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 23

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Paragraph
Number
14.1 Overview .................................................................................................................................... 14-1
14.2 Features ...................................................................................................................................... 14-1
14.3 Module Description ................................................................................................................... 14-1
14.4 Operation ................................................................................................................................... 14-3
14.5 Programming Model .................................................................................................................. 14-9
15.1 Overview .................................................................................................................................... 15-1
15.2 Timer Operation ......................................................................................................................... 15-1
15.3 General-Purpose Timer Registers .............................................................................................. 15-3
Freescale Semiconductor
14.3.1 Interface and Pins ........................................................................................................... 14-3
14.3.2 Internal Bus Interface ..................................................................................................... 14-3
14.4.1 QSPI RAM ..................................................................................................................... 14-4
14.4.2 Baud Rate Selection ....................................................................................................... 14-6
14.4.3 Transfer Delays ............................................................................................................... 14-7
14.4.4 Transfer Length .............................................................................................................. 14-8
14.4.5 Data Transfer .................................................................................................................. 14-8
14.5.1 QSPI Mode Register (QMR) .......................................................................................... 14-9
14.5.2 QSPI Delay Register (QDLYR) ................................................................................... 14-11
14.5.3 QSPI Wrap Register (QWR) ........................................................................................ 14-12
14.5.4 QSPI Interrupt Register (QIR) ...................................................................................... 14-13
14.5.5 QSPI Address Register (QAR) ..................................................................................... 14-14
14.5.6 QSPI Data Register (QDR) .......................................................................................... 14-14
14.5.7 Command RAM Registers (QCR0–QCR15) ............................................................... 14-15
14.5.8 Programming Example ................................................................................................. 14-16
15.3.1 Timer Mode Registers (TMR0–TMR3) .......................................................................... 15-3
15.3.2 Timer Reference Registers (TRR0–TRR3) .................................................................... 15-4
15.3.3 Timer Capture Registers (TCAP0–TCAP3) ................................................................... 15-4
15.3.4 Timer Counters (TCN0–TCN3) ..................................................................................... 15-4
15.3.5 Timer Event Registers (TER0–TER3) ........................................................................... 15-5
14.4.1.1 Receive RAM ................................................................................................... 14-5
14.4.1.2 Transmit RAM .................................................................................................. 14-6
14.4.1.3 Command RAM ............................................................................................... 14-6
Queued Serial Peripheral Interface (QSPI) Module
MCF5272 ColdFire
Table of Contents (Continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Timer Module
Chapter 14
Chapter 15
Title
Number
Page
xxiii