MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 175
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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Chapter 7
Interrupt Controller
This chapter describes the operation of the interrupt controller portion of the system integration module
(SIM). It includes descriptions of the registers in the interrupt controller memory map and the interrupt
priority scheme.
7.1
The SIM provides a centralized interrupt controller for all MCF5272 interrupt sources, which consist of
the following:
Figure 7-1
The SIM provides the following registers for managing interrupts:
Freescale Semiconductor
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External interrupts INT[6:1]
Timer modules
UART modules
PLIC module
USB module
DMA module
Ethernet module
QSPI module
Software watchdog timer (SWT)
Four interrupt control registers (ICR1–ICR4), which are used to assign interrupt levels to the
interrupt sources.
The interrupt source register (ISR) allows reading the instantaneous value of each interrupt source.
The programmable interrupt transition register (PITR) specifies the triggering transition of the
external interrupt inputs.
The programmable interrupt wakeup register (PIWR) specifies which interrupt sources can
reactivate the CPU from low-power sleep or stop mode.
The programmable interrupt vector register (PIVR) specifies which vector number is returned in
response to an interrupt acknowledge cycle.
Overview
is a block diagram of the interrupt controller.
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
7-1
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