MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 409

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

18.3.1
This register, shown in
re-enabled, writing to PWCR while the PWM is running will not alter its operation until the current output
cycle finishes. For example, if the prescale value is changed while the PWM is enabled, the new value will
not take effect until after the counter has “wrapped around”. The PWM must be disabled and then
re-enabled to affect its operation before the end of the current output cycle.
Table 18-2
Freescale Semiconductor
Bits
3–0
7
6
5
4
Name
FRC1
CKSL
LVL
EN
gives PWCR field descriptions.
—
PWM Control Register (PWCRn)
Enable.
0 Disables the PWM. While disabled, the PWM is in low-power mode and the prescaler does not count.
1 Enables the PWM.
Force output high.
0 Default reset value. PWM functions normally.
1 The PWM drives the output high for the entire counter period. PWCRn[FRC1] has a lower priority than
Disable level. Determines the PWM output level whenever the PWM is disabled.
0 The PWM output is low while disabled.
1 The PWM output is high while disabled.
Reserved, should be cleared.
Prescale clock. These bits select the clock frequency divider, that is, the output of the divider chain, as
shown below.
CKSL[3:0] Divisor
Address
When the PWM is disabled, the output is forced to the value of PWCRn[LVL].
PWCRn[EN], so setting PWCRn[FRC1] while PWCRn[EN] is cleared has no effect. There are two ways
to drive the PWM output high. If PWCRn[EN] is cleared, PWM output immediately assumes the value of
PWCRn[LVL]. If PWCRn[FRC1] is set while PWCRn[EN] is set, the PWM output does not go high until
after the current output cycle completes.
Reset
Field
R/W
MCF5272 ColdFire
0000 1
0001 2
0010 4
... ...
111132768
Figure
EN
7
MBAR + 0x0C0 (PWCR0); + 0x0C4 (PWCR1); + 0x0C8 (PWCR2)
Figure 18-2. PWM Control Registers (PWCRn)
18-2, controls the overall operation of the PWM. Unless disabled and then
Table 18-2. PWCRn Field Descriptions
FRC1
6
®
Integrated Microprocessor User’s Manual, Rev. 3
LVL
5
—
4
0010_0000
Read/Write
Description
3
CKSEL
Pulse-Width Modulation (PWM) Module
0
18-3