MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 185

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Chapter 8
Chip Select Module
This chapter describes the chip select module, including the chip select registers, the configuration and
behavior of the chip select signals, and the global chip select functions.
8.1
The chip select module provides user-programmable control of the eight chip select and four byte strobe
outputs. This subsection describes the operation and programming model of the chip select registers,
including the chip select base and option registers.
8.1.1
The following list summarizes the key chip select features:
8.1.2
Each of the eight chip selects, CS0–CS7, is configurable for external SRAM, ROM, and peripherals. CS0
is used to access external boot ROM and is enabled after a reset. The data bus width of the external ROM
must be configured at reset by having appropriate pull-down resistors on QSPI_CLK/BUSW1 and
QSPI_CS0/BUSW0. At reset these two signals replace the bus width field in the chip select 0 base register
(CSBR0[BW]).
CS7 must be used for enabling an external SDRAM array. In this mode, it is referred to as SDCS.
Freescale Semiconductor
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Eight dedicated programmable chip selects
Address masking for memory block sizes from 4 Kbytes to 2 Gbytes
Programmable wait states and port sizes
Programmable address setup
Programmable address hold for read and write
SDRAM controller interface supported with CS7/SDCS
Global chip select functionality
Overview
Features
Chip Select Usage
A detailed description of each bus access type supported by the MCF5272
device is given in
MCF5272 ColdFire
Chapter 20, “Bus
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
Operation.”
8-1