MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 98
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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ColdFire Core
If a ColdFire processor encounters any type of fault during the exception processing of another fault, the
processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to
force the processor to exit this halted state.
2-30
Exception
Exception
Exception
Interrupt
Reset
Interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized and
spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector.
Asserting the reset input signal (RSTI) causes a reset exception. Reset has the highest exception priority; it
provides for system initialization and recovery from catastrophic failure. When assertion of RSTI is recognized,
current processing is aborted and cannot be recovered. The reset exception places the processor in supervisor
mode by setting SR[S] and disables tracing by clearing SR[T]. This exception also clears SR[M] and sets the
processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to
0x0000_0000. Configuration registers controlling the operation of all processor-local memories (cache and
RAM modules on the MCF5272) are invalidated, disabling the memories.
Note: Other implementation-specific supervisor registers are also affected. Refer to each of the modules in this
If the processor is not halted and it has ownership of the bus, it initiates the reset exception by performing two
longword read bus cycles. The longword at address 0 is loaded into the stack pointer and the longword at
address 4 is loaded into the PC. After the initial instruction is fetched from memory, program execution begins
at the address in the PC. If an access error or address error occurs before the first instruction executes, the
processor enters the fault-on-fault halted state.
manual for details on these registers.
MCF5272 ColdFire
Table 2-21. MCF5272 Exceptions (continued)
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Freescale Semiconductor
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