MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 453
![](/photos/31/37/313782/mcf5272vf66_sml.jpg)
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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Figure 20-2
The four bytes shown are connected through the internal data bus and data multiplexer to the external data
bus. This path is how the MCF5272 supports programmable port sizing and operand misalignment. The
data multiplexer establishes the necessary connections for different combinations of address and data
sizes.
The multiplexer takes the four bytes of the 32-bit bus and routes them to their required positions. For
example, OP3 can be routed to D[7:0], as would be the normal case when interfacing to a 32-bit port. OP3
can be routed to D[23:16] for interfacing to a 16-bit port, or it can be routed to D[31:24] for interfacing to
an 8-bit port. The operand size, address, and port size of the memory being accessed determines the
positioning of bytes.
Freescale Semiconductor
REGISTER
MULTIPLEXER
EXTERNAL
ADDRESS
DATA BUS
shows the required organization of data ports on the MCF5272 for 8-, 16-, and 32 bit devices.
31
A1
OP0
0
0
1
0
0
1
1
MCF5272 ColdFire
A0
Figure 20-2. MCF5272 Interface to Various Port Sizes
0
0
0
0
1
0
1
Figure 20-1. Internal Operand Representation
OP1
D[31:24]
BYTE 0
BYTE 0
BYTE 2
BYTE 0
BYTE 1
BYTE 2
BYTE 3
OP0
®
ROUTING AND DUPLICATION
Integrated Microprocessor User’s Manual, Rev. 3
15
OP2
D[23:16]
OP2
BYTE 1
BYTE 1
BYTE 3
OP1
8-BIT PORT
7
BYTE 2
D[15:8]
OP3
OP3
OP2
OP3
16-BIT PORT
0
0
0
BYTE 3
D[7:0]
OP3
LONGWORD OPERAND
BYTE OPERAND
WORD OPERAND
32-BIT PORT
INTERNAL TO
MCF5272
Bus Operation
20-5
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