MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 158

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Debug Support
5.7.2
The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown
below. The PST/DDATA specification for these opcodes is shown in
The move-to-SR and RTE instructions include an optional PST = 0x3 value, indicating an entry into user
mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a
multiple-cycle status of 0xD is signaled.
Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xF)
display this status throughout the entire time the ColdFire processor is in the given mode.
5-40
Instruction
move.w
move.w
wdebug
cpushl
movec
stop
halt
rte
Supervisor Instruction Set
Operand Syntax
Table 5-23. PST/DDATA Specification for Supervisor-Mode Instructions
{Dy,#imm},SR
SR,Dx
<ea>y
Ry,Rc
#imm
MCF5272 ColdFire
operand},
PST = 0x1
PST = 0x1,
PST = 0xF
PST = 0x1
PST = 0x1, {PST = 0x3}
PST = 0x1
PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3}, { PST =0xB, DD =source
PST = 0x5, {[PST = 0x9AB], DD = target address}
PST = 0x1,
PST = 0xE
PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}
®
Integrated Microprocessor User’s Manual, Rev. 3
PST/DDATA
Table
5-23.
Freescale Semiconductor