MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 111
![](/photos/31/37/313782/mcf5272vf66_sml.jpg)
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66
Manufacturer:
HYNIX
Quantity:
19
Company:
Part Number:
MCF5272VF66
Manufacturer:
FREESCAL
Quantity:
885
Company:
Part Number:
MCF5272VF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5272VF66
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MCF5272VF66J
Manufacturer:
Freescale
Quantity:
256
Company:
Part Number:
MCF5272VF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCF5272VF66R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 111 of 544
- Download datasheet (7Mb)
Cache invalidation can be performed in the two following ways:
These invalidation operations can be initiated from the ColdFire core or the debug module.
4.5.2.3
For every memory reference generated by the processor or debug module, a set of effective attributes is
determined based on the address and the ACRs. Caching modes determine how the cache handles an
access. An access can be cacheable or cache-inhibited. For normal accesses, the ACRn[CM] bit
corresponding to the address of the access specifies the caching mode. If an address does not match an
ACR, the default caching mode is defined by CACR[DCM]. The specific algorithm is as follows:
if (address == ACR0-address including mask)
else if (address == ACR1-address including mask)
Addresses matching an ACR can also be write protected using ACR[WP].
Reset disables the cache and clears all CACR bits. Reset does not automatically invalidate cache entries;
they must be invalidated through software.
The ACRs allow CACR defaults to be overridden. In addition, some instructions (for example, CPUSHL)
and processor core operations perform accesses that have an implicit caching mode associated with them.
The following sections discuss the different caching accesses and their associated cache modes.
4.5.2.3.1
If ACRn[CM] or the default field of the CACR indicates the access is cacheable, a read access is read from
the cache if matching data is found. Otherwise, the data is read from memory and the cache is updated.
When a line is being read from memory, the longword in the line that contains the core-requested data is
loaded first and the requested data is given immediately to the processor, without waiting for the three
remaining longwords to reach the cache.
4.5.2.3.2
Memory regions can be designated as cache-inhibited, which is useful for memory containing targets such
as I/O devices and shared data structures in multiprocessing systems. Do not cache memory-mapped
registers (for example, registers shown with an MBAR offset). If the corresponding ACRn[CM] or
CACR[DCM] indicates cache-inhibited the access is cache-inhibited. The caching operation is identical
for both cache-inhibited modes, which differ only regarding recovery from an external bus error.
Freescale Semiconductor
•
•
Setting CACR[CINVA] forces the entire instruction cache to be marked as invalid. The
invalidation operation requires 64 cycles because the cache sequences through the entire tag array,
clearing a single location each cycle. Any subsequent instruction fetch accesses are postponed until
the invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is
executed, the cache entry defined by bits 9–4 of the source address register is invalidated, provided
CACR[CDPI] is cleared.
effective attributes = ACR0 attributes
else effective attributes = CACR default attributes
Caching Modes
Cacheable Accesses
Cache-Inhibited Accesses
effective attributes = ACR1 attributes
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Local Memory
4-9
Related parts for MCF5272VF66
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![mcf5272](/images/manufacturer_photos/0/2/263/freescale_semiconductor__inc_tmb.jpg)
Part Number:
Description:
Mcf5272 Coldfire Integrated Microprocessor User
Manufacturer:
Freescale Semiconductor, Inc
Datasheet:
![AN2184](/images/no-image3.png)
Part Number:
Description:
MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller
Manufacturer:
Freescale Semiconductor / Motorola
Datasheet:
![TWR-ELEV](/photos/9/0/90062/twr-elev_inside_tmb.jpg)
Part Number:
Description:
TOWER ELEVATOR BOARDS HARDWARE
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-SER](/photos/9/0/90065/twr-ser_tmb.jpg)
Part Number:
Description:
TOWER SERIAL I/O HARDWARE
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-LCD](/photos/37/59/375952/twr-lcd_bd_tmb.jpg)
Part Number:
Description:
LCD MODULE FOR TWR SYSTEM
Manufacturer:
Freescale Semiconductor
Datasheet:
![MCIMX51LCD](/photos/37/58/375843/mx51-lcd_tmb.jpg)
Part Number:
Description:
DAUGHTER LCD WVGA I.MX51
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-MPC5125](/photos/37/59/375933/twrmpc5125_tmb.jpg)
Part Number:
Description:
TOWER SYSTEM BOARD MPC5125
Manufacturer:
Freescale Semiconductor
Datasheet:
![MCIMX51EVKJ](/photos/9/23/92399/mcimx51evkj_tmb.jpg)
Part Number:
Description:
KIT EVALUATION I.MX51
Manufacturer:
Freescale Semiconductor
Datasheet:
![MCIMX25WPDKJ](/photos/37/58/375856/imx25pdk_bd_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT WINCE IMX25
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-MPC5125-KIT](/photos/9/25/92581/mfg_twr-mpc5125-kit_tmb.jpg)
Part Number:
Description:
TOWER SYSTEM KIT MPC5125
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-K40X256](/photos/30/35/303578/twr-kx0n_tmb.jpg)
Part Number:
Description:
TOWER SYSTEM BOARD K40X256
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-K40X256-KIT](/photos/37/58/375861/twr-kx0n-kit_tmb.jpg)
Part Number:
Description:
TOWER SYSTEM KIT K40X256
Manufacturer:
Freescale Semiconductor
Datasheet:
![MCIMX28EVK](/photos/16/13/161325/imx28_tmb.jpg)
Part Number:
Description:
Microcontrollers (MCU) MX28 PLATFORM DEV KIT
Manufacturer:
Freescale Semiconductor
Datasheet:
![TWR-K60N512-IAR](/photos/18/26/182613/twr-kx0n_tmb.jpg)
Part Number:
Description:
MCU, MPU & DSP Development Tools IAR KickStart Kit for Kinetis K60
Manufacturer:
Freescale Semiconductor
Datasheet:
![MCIMXHDMICARD](/photos/40/32/403220/mcimxhdmicard_tmb.jpg)
Part Number:
Description:
24BIT HDMI MX535/08
Manufacturer:
Freescale Semiconductor
Datasheet: