MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 315

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
14–12
Bits
10
15
11
8
7
3
2
0
9
1
ON/OFF 0 Port is off and in a steady state condition. In this state, the B and D channels on the transmit side are
Name
SHB2
SHB1
ENB2
ENB1
DMX
FSM
ACT
M/S
G/S
M
1 Switches on the port for operation in the configured mode.
Mode. Selects between various modes of operation as described below. Note: bit 14 is relevant to port 0
only. The IDL modes on the PLIC only support short frame sync.
Port 1-3 Port 0
000 IDL8IDL8
001 IDL10IDL10
010 GCIGCI
011 ReservedReserved
10x ReservedReserved
11x ReservedReserved
Master/Slave. Defines the direction of the DCL1 and FSC1 pins.
0 DCL1 and FSC1 are inputs and are sourced from an external master. Note: This bit is relevant to port 1
1 enables DCL1 and FSC1 to be outputs, that is, the MCF5272 drives DCL1 and FSC1.
GCI/SCIT.
0 The normal mode of GCI is used (i.e. no D-channel contention control).
1 Selects SCIT mode of operation for the GCI interfaces.
Frame Sync Master.
0 Default reset value. 2-KHz interrupt is generated from port 0.
1 Port 1 FSC/FSR is used to generate the 2-KHz interrupt.
GCI Activation.
0 Default reset value.
1 Causes Dout to transition to a logic low for the respective port. This bit is only operational when the port
is in GCI mode. Setting the ACT bit in any other mode has no effect. It is the responsibility of the CPU to
clear the ACT bit when normal operation on Dout is required. This bit is intended to be used to request
activation from the upstream DCL/FSC driver. Periodic interrupts commence as soon as the upstream
device generates DCL, provided the appropriate interrupts, such as IE, B1RIE, and so on, are enabled for
the port.
Data multiplex.
0 port 3 Dout and Din are multiplexed onto Dout1 and Din1.
1 enables port 3 Dout and Din to be connected to dedicated output and input pins, DOUT3 and DIN3.
B2 channel shift direction.
0 B2 channel data is received/transmitted msb first. The msb-first convention is often used for
1 B2 channel data is received/transmitted lsb first. The lsb-first convention is used when the data is to be
B1 channel shift direction. See SHB2.
Enable B2 data channel.
0 The B2 channel is disabled and all periodic interrupts in both receive and transmit directions are
1 Enables the B2 data channel for the respective port.
Enable B1 data channel. See ENB2.
high impedance when in GCI/IDL. The receive registers are all set. In IDL and GCI modes with the port
in this state, all periodic and aperiodic interrupts associated with the port are disabled.
only, as port 0 is always in slave mode.
communication with PCM CODECs and converters.
HDLC encoded.
disabled. The behavior of Din and Dout in this state is shown below.
MCF5272 ColdFire
Mode
GCI
IDL
Table 13-2. P0CR–P3CR Field Descriptions
Operational (data on Din visible) Open drain
All 1s
®
Integrated Microprocessor User’s Manual, Rev. 3
Din
Description
High Impedance
Dout
Physical Layer Interface Controller (PLIC)
13-19