MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 502

MCF5272VF66

Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet

Specifications of MCF5272VF66

Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant

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Electrical Characteristics
23.6.2
Table 23-12
The transmitter functions correctly up to a E_TxCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
E_TxCLK frequency.
The transmit outputs (E_TxD[3:0], E_TxEN, E_TxER) can be programmed to transition from either the
rising or falling edge of E_TxCLK, and the timing is the same in either case. This options allows the use
of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
1
Figure 23-12
23-18
E_TxCLK, ETxD0, and E_TxEN have the same timing in 10 Mbit 7-wire interface mode.
Num
M5
M6
M7
M8
E_TxCLK to E_TxD[3:0], E_TxEN, E_TxER invalid
E_TxCLK to E_TxD[3:0], E_TxEN, E_TxER valid
E_TxCLK pulse-width high
E_TxCLK pulse-width low
E_TxD[3:0] (outputs)
MII Transmit Signal Timing (E_TxD[3:0], E_TxEN, E_TxER,
E_TxCLK)
lists MII transmit channel timings.
E_TxCLK (input)
shows MII transmit signal timings listed in
E_TxEN
E_TxER
MCF5272 ColdFire
Figure 23-12. MII Transmit Signal Timing Diagram
Characteristic
Table 23-12. MII Transmit Signal Timing
®
Integrated Microprocessor User’s Manual, Rev. 3
1
M5
M6
M7
Table
23-12.
M8
5
35%
35%
Min
25
65%
65%
Max
Freescale Semiconductor
nS
nS
E_TxCLK period
E_TxCLK period
Unit

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