MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 165

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

6.2.3
The system configuration register (SCR),
system features.
Table 6-3
Freescale Semiconductor
13–12
15-14
11–9
Bits
5–4
8
7
6
Address
Reset 1
Field 1
RSTSRC Reset source. Indicates the source of the last device reset.
SoftRST
R/W
Priority
describes SCR fields.
Field
AR
—
—
—
System Configuration Register (SCR)
15
14
0
0
Reserved. Bit 15 always reads as a 1, bit 14 as a 0. Writing to these bits has no effect.
00 Reserved
01 RSTI asserted, DRESETEN not asserted
10 Software watchdog
11 RSTI and DRESETEN asserted
Reserved, should be cleared.
Selects the bus arbiter priority scheme.
0 Ethernet has highest priority, DMA has next highest priority, CPU has lowest priority.
1 CPU has highest priority, DMA has next highest priority, Ethernet has lowest priority.
This bit should be cleared if the Ethernet module is enabled.
Assume request. Selects the bus mastership scheme.
0 Current bus master relinquishes the bus after the current bus cycle.
1 Assume current bus master wants the bus for the next bus cycle and include it in the arbitration process.
Writing a one to this bit resets the on-chip peripherals, excluding the chip select module, interrupt
controller module, GPIO module, and SDRAM controller, and asserts RSTO. The CPU is not reset. The
reset remains asserted for 128 clock cycles. This bit is automatically cleared on negation of the reset.
Reserved, should be cleared.
If AR is set and the current bus master has a higher priority than other requesting masters but is not
requesting the bus for the next cycle, there is a 1 clock dead cycle before the arbiter can reassign the
bus to the next highest priority master.
MCF5272 ColdFire
seeTable 6-3
13
RSTSRC
Figure 6-3. System Configuration Register (SCR)
12
R/W; except for RSTSRC[1:0], which are read only
Table 6-3. SCR Field Descriptions
11
®
—
Integrated Microprocessor User’s Manual, Rev. 3
Figure
9
Priority
8
6-3, provides information and control for a variety of
MBAR + 0x004
AR SoftRST
7
Description
0000_1000_0111
6
5
—
4
BusLock
3
System Integration Module (SIM)
2
HWR
0
6-5