MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 163

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

6.2.2
The supervisor-level MBAR,
internal peripherals. It is written with a MOVEC instruction using the CPU address 0xC0F. (See the
ColdFire Family Programmer’s Reference Manual.) MBAR can be read or written through the debug
module as a read/write register, as described in.” Once MBAR has been initialized, it can be read and
written in supervisor mode at the address programmed into the base address (BA) field.
The valid bit, MBAR[V], is cleared at system reset to prevent incorrect references before MBAR is
written; other MBAR bits are uninitialized at reset. To access internal peripherals, write MBAR with the
appropriate base address (BA) and set MBAR[V] after system reset.
All internal peripheral registers occupy a single relocatable memory block along 64-Kbyte boundaries. If
MBAR[V] is set, MBAR[BA] is compared to the upper 16 bits of the full 32-bit internal address to
Freescale Semiconductor
0x014–
MBAR
Offset
0x00C
0x01C
0x02C
0x03C
0x28C
0x000
0x004
0x008
0x010
0x020
0x024
0x028
0x030
0x034
0x038
0x280
0x284
0x288
Watchdog interrupt reference register (WIRR) [p. 6-12]
Module Base Address Register (MBAR)
Watchdog reset reference register (WRRR) [p. 6-12]
System configuration register (SCR) [p. 6-5]
Watchdog counter register (WCR) [p. 6-13]
Watchdog event register (WER) [p. 6-13]
[31:24]
MCF5272 ColdFire
Figure
Reserved
Module base address register (MBAR), after initialization [p. 6-3]
Programmable interrupt transition register (PITR) [p. 7-7]
Programmable interrupt wakeup register (PIWR) [p. 7-8]
6-2, specifies the base address and allowable access types for all
®
Integrated Microprocessor User’s Manual, Rev. 3
Power management register (PMR) [p. 6-7]
Device identification register (DIR) [p. 6-11]
Software Watchdog Registers
Interrupt Controller Registers
Table 6-1. SIM Registers
Interrupt control register 1 (ICR1) [p. 7-4]
Interrupt control register 2 (ICR2) [p. 7-5]
Interrupt control register 3 (ICR3) [p. 7-5]
Interrupt control register 4 (ICR4) [p. 7-5]
Reserved
Interrupt source register (ISR) [p. 7-6]
[23:16]
Reserved
Active low power register (ALPR) [p. 6-10]
System protection register (SPR) [p. 6-6]
[15:8]
Reserved
Reserved
Reserved
Reserved
System Integration Module (SIM)
vector register (PIVR) [p.
Programmable interrupt
[7:0]
7-9]
6-3