MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 112

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Local Memory
In determining whether a memory location is cacheable or cache-inhibited, the CPU checks
memory-control registers using the following priority:
Cache-inhibited write accesses bypass the cache and a corresponding external write is performed.
Cache-inhibited reads bypass the cache and are performed on the external bus, except when all of the
following conditions are true:
In this case, a fetched line is stored in the fill buffer and remains valid there; the cache can service
additional read accesses from this buffer until another fill occurs or a cache-invalidate-all operation occurs.
If ACRn[CM] indicates cache-inhibited, the controller bypasses the cache and performs an external
transfer. To ensure the consistency of cached data, execute a CPUSHL instruction or set CACR[CINVA]
to invalidate the entire cache before switching cache modes.
CPU space-register accesses, such as MOVEC, are treated as cache-inhibited.
4.5.2.4
A hardware reset clears the CACR disabling the instruction cache.
4.5.2.5
As discussed in
includes a 16-byte line-fill buffer for providing temporary storage for the last fetched instruction.
With the cache enabled as defined by CACR[CENB], a cacheable instruction fetch that misses in both the
tag memory and the line-fill buffer generates an external fetch. The size of the external fetch is determined
by the value contained in CACR[CLNF] and the miss address.
the CLNF bits, the miss address, and the size of the external fetch.
Depending on the run-time characteristics of the application and the memory response speed, overall
performance may be increased by programming CLNF to values {00, 01}.
4-10
1. RAMBAR
2. ROMBAR
3. ACR0
4. ACR1
5. If an access does not hit in RAMBAR, ROMBAR, or the ACRs, the default is provided for all
•
•
•
accesses in CACR.
The cache-inhibited fill-buffer bit, CACR[CEIB], is set.
The access is an instruction read.
The access is normal (that is, TT = 0).
Reset
Cache Miss Fetch Algorithm/Line Fills
Tag array contents are not affected by reset. Accordingly, system startup
code must explicitly invalidate the cache by setting CACR[CINVA] before
the cache can be enabled.
Section 4.5.1, “Instruction Cache Physical
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
Organization,” the instruction cache hardware
Table 4-8
shows the relationships between
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