MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 323

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

13.5.15 GCI Monitor Channel Transmit Status Register (PGMTS)
All bits in this register are read only and are cleared on hardware or software reset.
The PGMTS register contains the monitor channel status bits for each of the four transmit ports on the
MCF5272.
Freescale Semiconductor
Bits
7
6
5
4
3
2
1
0
Name
ACK3 Acknowledge, port 3.
ACK2 Acknowledge, port 2. See ACK3.
ACK1 Acknowledge, port 1. See ACK3.
ACK0 Acknowledge, port 0. See ACK3.
AB3
AB2
AB1
AB0
0 Default reset value.
1 Indicates to the CPU that the GCI controller has transmitted the previous monitor channel information.
Abort, port 3.
0 Default reset value.
1 Indicates to the CPU that the GCI controller has aborted the current message. This bit is automatically
Abort, port 2. See AB3.
Abort, port 1. See AB3.
Abort, port 0. See AB3.
Automatically cleared by the CPU reading the register. The clearing of this bit by reading this register also
clears the aperiodic GMT interrupt.
cleared by the CPU reading the register. When the GCI controller sets this bit, it also clears the AR bit in the
PGMTA register, the ACK bit in the GMTS register, and the L and R bits in the PnGMT register.
Figure 13-27. GCI Monitor Channel Transmit Status Register (PGMTS)
Reset
Field ACK3
Addr
R/W
MCF5272 ColdFire
7
Table 13-10. PGMTS Field Descriptions
ACK2
6
®
Integrated Microprocessor User’s Manual, Rev. 3
ACK1
5
ACK0
MBAR + 0x371
0000_0000
Read Only
4
Description
AB3
3
AB2
2
Physical Layer Interface Controller (PLIC)
AB1
1
AB0
0
13-27