MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 517

MCF5272VF66

Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet

Specifications of MCF5272VF66

Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant

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Appendix A
List of Memory Maps
The MCF5272 memory map is given in this section.
The addresses for the system configuration registers are absolute addresses in the MCF5272 CPU space
memory map. The on-chip peripheral modules are configured as a group by programming the module base
address register, (MBAR).
In the title block for each module is shown the offset address of the given register from the base address
programmed in MBAR.
The following formula allows calculation of the absolute address of a given register.
Absolute address = MBAR + register offset
A.1
Freescale Semiconductor
List of Memory Map Tables
Configuration Registers
Interrupt Registers
Chip Select Registers
Ports Registers
QSPI Module Registers
PWM Module Registers
DMA Module Registers
UART0 Module Registers
UART1 Module Registers
SDRAM Controller Registers
Timer Module Registers
PLIC Module Registers
Ethernet Module Registers
USB Module Registers
MCF5272 ColdFire
Table A-1. On-Chip Module Base Address Offsets from MBAR
Module
®
Integrated Microprocessor User’s Manual, Rev. 3
MBAR+0x0000
MBAR+0x0020
MBAR+0x0040
MBAR+0x0080
MBAR+0x00A0
MBAR+0x00C0
MBAR+0x00E0
MBAR+0x0100
MBAR+0x0140
MBAR+0x0180
MBAR+0x0200
MBAR+0x0300
MBAR+0x0800
MBAR+0x1000
Module Base
Address
CFG_Base
INT_Base
CS_Base
GPIO_Base
QSPI_Base
PWM_Base
DMAC_Base
UART0_Base
UART1_Base
SDRAMC_Base
Timer_Base
PLIC_Base
ENET_Base
USB_Base
Mnemonic
A-1

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