MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 153

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. All
interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use
supervisor instructions to save the necessary context such as the state of all program-visible registers into
a reserved memory area.
When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator
mode. After the debug interrupt handler completes execution, the external development system can use
BDM commands to read the reserved memory locations.
If a hardware breakpoint such as a PC trigger is left unmodified by the debug interrupt service routine,
another debug interrupt is generated after the completion of the RTE instruction.
5.6.1.1
Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be entered in three
different ways:
While operating in emulation mode, the processor exhibits the following properties:
The RTE instruction exits emulation mode. The processor status output port provides a unique encoding
for emulator mode entry (0xD) and exit (0x7).
5.6.2
The debug module supports concurrent operation of both the processor and most BDM commands. BDM
commands may be executed while the processor is running, except those following operations that access
processor/memory registers:
For BDM commands that access memory, the debug module requests the processor’s local bus. The
processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to
complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
Freescale Semiconductor
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Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is
negated and the processor begins reset exception processing. It can be set while the processor is
halted before reset exception processing begins. See
A debug interrupt always puts the processor in emulation mode when debug interrupt exception
processing begins.
Setting CSR[TRC] forces the processor into emulation mode when trace exception processing
begins.
All interrupts are ignored, including level-7 interrupts.
If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory
accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5 or 0x6.
This includes stack frame writes and the vector fetch for the exception that forced entry into this
mode.
Read/write address and data registers
Read/write control registers
Concurrent BDM and Processor Operation
Emulator Mode
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Section 5.5.1, “CPU
Halt.”
Debug Support
5-35