MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 303

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Because the presentation of HDLC encoded data on the physical interface is lsb first, the lsb is
right-aligned in the transmit and receive shift register.
A D-channel byte is formed by concatenating two D bits from each of four frames. This data is also
right-aligned in the D-channel receive register as shown in
13.2.3.4
As with the B channel, a mechanism is provided to support incoming D channels containing unencoded
data, even though as of this document’s publication date, no communication protocols using unencoded
D-channel data are known.
As with unencoded (PCM encoded) B-channel data, it is assumed unencoded D-channel information is
presented on the physical line msb first. The msb is left-aligned in the transmit and receive shift register,
that is, the first bit received is aligned in the msb position through to the last received bit of a byte that is
aligned in the lsb position.
A D-channel byte is formed by concatenating two D bits from each frame over four consecutive frames as
shown in
two D-channel bits from the first frame go into the two msbs, B
the second frame in B
in B
Freescale Semiconductor
1
and B
DCL
FSR
Figure
Unencoded
HDLC
Encoded
Din/Dout
Din/Dout
0
.
D-Channel Unencoded Data
13-7. These 8 bits are also left-aligned in the D-channel receive register, that is, the first
Frame 0
5
MCF5272 ColdFire
Figure 13-7. D-Channel HDLC Encoded and Unencoded Data.
and B
D
D
0
7
8-Bit D-Channel Receive/Transmit Register, RD, TD
Frame
D
D
1
6
4
, and so on, until the last two D-channel bits in the fourth frame are aligned
D7
®
Frame 1
Integrated Microprocessor User’s Manual, Rev. 3
3
D6
D
D
2
5
D5
D
D
3
4
2
D4
D3
Figure
Frame 2
1
7
D2
and B
D
D
13-7.
4
3
D1
D
D
5
2
6
0
, the next two D-channel bits from
Physical Layer Interface Controller (PLIC)
D0
Frame 3
D
D
6
1
D
D
7
0
13-7