MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 64

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Overview
1.2
This section briefly describes the MCF5272 core, SIM, UART, and timer modules, and test access port.
1.2.1
Based on the concept of variable-length RISC technology, ColdFire combines the simplicity of
conventional 32-bit RISC architectures with a memory-saving, variable-length instruction set. The main
features of the MCF5272 core are as follows:
1-4
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System integration module (SIM)
— System configuration including internal and external address mapping
— System protection by hardware watchdog
— Versatile programmable chip-select signals with wait-state generation logic
— Up to three 16-bit parallel input/output ports
— Latchable interrupt inputs with programmable priority and edge triggering
— Programmable interrupt vectors for on-chip peripherals
Physical layer interface controller (PLIC)
— Allows connection using general circuit interface (GCI) or interchip digital link (IDL) physical
— Three physical interfaces
— Four time-division multiplex (TDM) ports
IEEE 1149.1 boundary-scan test access port (JTAG) for board-level testing
Operating voltage: 3.3 V ±0.3 V
Operating temperature: 0 –70°C
Operating frequency: DC to 66 MHz, from external CMOS oscillator
Compact ultra low-profile 196 ball-molded plastic ball-grid array package (PGBA)
32-bit address bus directly addresses up to 4 Gbytes of address space
32-bit data bus
Variable-length RISC
Optimized instruction set for high-level language constructs
Sixteen general-purpose 32-bit data and address registers
MAC unit for DSP applications
Supervisor/user modes for system protection
Vector base register to relocate exception-vector table
Special core interfacing signals for integrated memories
Full debug support
MCF5272 Architecture
layer protocols for 2B + D data
Version 2 ColdFire Core
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor