MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 166
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MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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System Integration Module (SIM)
6.2.4
The system protection register (SPR),
generated error conditions. These error conditions can optionally generate an access error exception by
using the enable bits.
Table 6-4
6-6
15, 7
14, 6
13, 5
12, 4
Bits
Bits
2–0
3
PE, PEEN Peripheral error. This bit is set when an access to an on-chip peripheral is terminated with a transfer error.
WPVEN
ADCEN
SMVEN
BusLock
Fields
WPV,
ADC,
SMV,
describes SPR fields.
Field
HWR
System Protection Register (SPR)
Address
Reset
Reset
Field
Field ADCEN
R/W
R/W
Locks the ownership of the bus.
0 Ownership of the bus is determined by arbitration.
1 Current bus master retains ownership of the bus indefinitely.
Hardware watchdog reference. Determines how many clocks to wait before timing out a bus cycle when
SPR[HWTEN] is set. The value programmed should be longer than the response time of the slowest
external peripheral in the system.
000 128
001 256
010 512
011 1024
100 2048
101 4096
110 8192
111 16384
Address decode conflict. This bit is set when an address matches against two chip selects. If ADCEN is
also set, the bus cycle is terminated with an access error exception.
Write protect violation. This bit is set when a write access is attempted to an area for which the chip select
is set to read only. If WPVEN is also set, the bus cycle is terminated with an access error exception.
Stopped module violation. This bit is set when an access is attempted to an on-chip peripheral whose
clock has been stopped. If SMVEN is also set, the bus cycle is terminated with an access error exception.
If PEEN is also set, the bus cycle is terminated with an access error exception.
MCF5272 ColdFire
ADC
15
7
Table 6-3. SCR Field Descriptions (continued)
Figure 6-4. System Protection Register (SPR)
WPVEN
WPV
14
6
Table 6-4. SPR Field Descriptions
Figure
®
SMVEN
Integrated Microprocessor User’s Manual, Rev. 3
SMV
13
5
6-4, provides information about bus cycles that have
PEEN
MBAR + 0x006
PE
12
4
0000_0000
0000_1011
R/W
R/W
Description
Description
HWTEN
HWT
11
3
RPVEN
RPV
10
2
EXTEN
EXT
9
1
Freescale Semiconductor
SUVEN
SUV
8
0
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