MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 283

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

12.3.2.16 USB Endpoints 1–7 Status / Interrupt Registers (EPnISR)
Figure 12-19
Table 12-15
Freescale Semiconductor
12–5
Bits
15
14
13
4
3
2
Reset
Field HALT_ST DIR PRES
Addr
R/W
lists field descriptions for the USB endpoints 1–7 interrupt status registers.
HALT_ST
UNHALT
shows the USB endpoints 1-7 status/interrupt registers.
Name
PRES
EOP
EOT
DIR
—
Interrupt bits are cleared by writing a 1 to the specified bits. Bits 13–15 are read-only status bits.
15
Figure 12-19. USB Endpoints 1–7 Interrupt Status Registers (EPnISR)
MCF5272 ColdFire
Current status of endpoint n. This bit indicates whether endpoint n is currently halted or active.
HALT_ST is set due to a SET_FEATURE request with the endpoint halt feature selector set or a
STALL response to an IN or OUT packet. HALT_ST is cleared by a CLEAR_FEATURE request with
the endpoint halt feature selector set.
0 Endpoint n active
1 Endpoint n halted
Current direction of endpoint n. This bit indicates whether endpoint n is currently configured as an
IN or OUT endpoint.
0 Endpoint n configured as an OUT endpoint
1 Endpoint n configured as an IN endpoint
Endpoint n present. This bit indicates whether or not endpoint n is present in the current
configuration.
0 Endpoint n absent
1 Endpoint n present
Reserved, should be cleared.
End of transfer interrupt. Set when the end of a transfer has been reached. An EOT interrupt is
generated when a packet with a size less than the maximum packet size or the first zero-length
packet following maximum size packets is sent or received. For OUT endpoints, the EPDPn must be
read before clearing this interrupt in order to determine the number of bytes of remaining data in the
FIFO for the last transfer. For OUT endpoints, any packets received from the host cause a NAK
response until the EOT interrupt is cleared. For IN endpoints, the user must wait until the EOT
interrupt is set before writing the next transfer to the FIFO.
0 No interrupt pending
1 Transfer completed
End of packet interrupt. Set when a packet is successfully sent or received on endpoint n.
0 No interrupt pending
1 Packet sent or received successfully
Endpoint unhalt interrupt. Set when the endpoint n HALT_ST bit is cleared.
0 No interrupt pending
1 Endpoint n unhalted
14
MBAR + 0x1072, 0x1076, 0x107A, 0x107E, 0x1082, 0x1086, 0x108A
13
Table 12-15. EPnISR Field Descriptions
12
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0000_0000_0000
—
Description
5
EOT EOP UNHALT HALT FIFO_LVL
4
3
2
Universal Serial Bus (USB)
1
0
12-25