MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 324

MCF5272VF66

Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet

Specifications of MCF5272VF66

Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5272VF66
Manufacturer:
HYNIX
Quantity:
19
Part Number:
MCF5272VF66
Manufacturer:
FREESCAL
Quantity:
885
Part Number:
MCF5272VF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5272VF66
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MCF5272VF66J
Manufacturer:
Freescale
Quantity:
256
Part Number:
MCF5272VF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5272VF66R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Physical Layer Interface Controller (PLIC)
13.5.16 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
All bits in these registers are read only and are cleared on hardware or software reset.
The PnGCIR registers contain the received C/I bits for one of each of the four ports on the MCF5272.
13-28
31–29, 23–21,
27–24, 19–16,
28, 20, 12, 4
15–13, 7–5
11–8, 3–0
Reset
Reset
Chan
Chan
Field
Field
Addr
R/W
R/W
Bits
31
15
C3–C0 C/I bits. These four bits are received on the GCI or SCIT channel 0. When a change in the C/I data
Name
Figure 13-28. GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
F
MCF5272 ColdFire
MBAR + 0x374 (P0GCIR), 0x375 (P1GCIR), 0x376 (P2GCIR), 0x377 (P3GCIR)
29
13
Reserved, should be cleared.
Full. This bit is set by the C/I channel controller to indicate to the CPU that new C/I channel data
has been received and is available for processing. It is automatically cleared by a CPU read. The
clearing of this bit by reading this register also clears the aperiodic GCR interrupt.
value is received in two successive frames, it is interpreted as being valid and is passed on to the
CPU, via this register. A maskable interrupt is generated when data is written into any of the four
available positions.
Table 13-11. P0GCIR–P3GCIR Field Descriptions
28
12
F
P0GCIR
F
P2GCIR
C3
C3
27
11
®
Integrated Microprocessor User’s Manual, Rev. 3
C2
C2
26
10
C1
0000_0000_0000_0000
C1
0000_0000_0000_0000
25
9
Read Only
Read Only
C0
C0
24
8
23
7
Description
21
5
20
F
P1GCIR
F
P3GCIR
4
C3
C3
19
3
Freescale Semiconductor
C2
C2
18
2
C1
C1
17
1
C0
C0
16
0

Related parts for MCF5272VF66