MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 297

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Chapter 13
Physical Layer Interface Controller (PLIC)
This chapter provides detailed information about the MCF5272’s physical layer interface controller
(PLIC), a module intended to support ISDN applications. The chapter begins with a description of
operation and a series of related block diagrams starting with a high-level overview. Each successive
diagram depicts progressively more internal detail. The chapter then describes timing generation, the
programming model, and concludes with three application examples.
The reader is assumed to have a basic familiarity with ISDN technology and terminology. A glossary
containing many ISDN terms can be found on the web at the following URL:
http://www.tribecatech.com/isdnterm.htm.
13.1
Introduction
The physical layer interface controller (PLIC) allows the MCF5272 to connect at a physical level with
external CODECs (coder/decoder) and other peripheral devices that use either the general circuit interface
(GCI) or interchip digital link (IDL) physical layer protocols. This module is primarily intended to
facilitate designs that include ISDN (integrated services digital network) interfaces.
The MCF5272 has four dedicated physical layer interface ports for connecting to external ISDN
transceivers, codecs, and other peripherals. There are three sets of pins for these interfaces. Port 0 has its
own dedicated set of pins. Ports 1, 2, and 3 share a set of pins. Port 3 can also be configured to use a
dedicated pin set. Ports 1, 2, and 3 always share the same data clock (DCL).
When the ports are operated in slave mode, the PLIC can support a DCL frequency of 4.096 MHz and
frame sync frequency (FSC/FSR) of 8 KHz. When in master mode, DCL should be no greater than
one-twentieth of the CPU clock (CLKIN), with a maximum FSC/FSR of 8 KHz.
This chapter is written from the perspective of connecting to an ISDN transceiver with 8-KHz frame sync.
The MCF5272 PLIC has four ports, port 0 – port 3, connected through three pin sets, numbered 0, 1, and 3.
A port can service, read, or write any 2B + D channel. As shown in
Figure
13-1, port 0 connects through
pin set 0, and ports 1 and 2 both connect through set 1. port 3 can use either pin set 1 or 3. Pin set 3 consists
of data in and data out. Data clock and frame sync are common to pin set 1 and 3. In the case of set 1, which
connects multiple ports, separate delayed frame sync generators are provided for each port which
distinguish each port’s active time slots. See
Section 13.6, “Application
Examples” for further
information.
®
MCF5272 ColdFire
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-1