MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 72
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MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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ColdFire Core
2.1.1.2.3
The hardware divide unit performs the following integer division operations:
2.1.2
The ColdFire processor core debug interface supports system integration in conjunction with low-cost
development tools. Real-time trace and debug information can be accessed through a standard interface,
which allows the processor and system to be debugged at full speed without costly in-circuit emulators.
On-chip breakpoint resources include the following:
These registers can be accessed through the dedicated debug serial communication channel, or from the
processor’s supervisor programming model, using the WDEBUG instruction.
2.2
The MCF5272 programming model consists of three instruction and register groups—user, MAC (also
user-mode), and supervisor, shown in
instructions and programming models. Supervisor-mode system software can reference all user-mode and
MAC instructions and registers and additional supervisor instructions and control registers. The user or
supervisor programming model is selected based on SR[S]. The following sections describe the registers
in the user, MAC, and supervisor programming models.
2.2.1
As
2-4
Figure 2-3
•
•
•
•
•
•
•
•
•
•
•
32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder
32-bit operand/32-bit operand producing a 32-bit quotient
32-bit operand/32-bit operand producing a 32-bit remainder
Configuration/status register (CSR)
Bus attributes and mask register (AATR)
Breakpoint registers. These can be used to define triggers combining address, data, and PC
conditions in single- or dual-level definitions. They include the following:
— PC breakpoint register (PBR)
— PC breakpoint mask register (PBMR)
— Data operand address breakpoint registers (ABHR/ABLR)
— Data breakpoint register (DBR)
Data breakpoint mask register (DBMR)
Trigger definition register (TDR) can be programmed to generate a processor halt or initiate a
debug interrupt exception
16 general-purpose 32-bit registers, D0–D7 and A0–A7
32-bit program counter
8-bit condition code register
Programming Model
Debug Module Enhancements
User Programming Model
shows, the user programming model consists of the following registers:
Hardware Divide Unit
MCF5272 ColdFire
Figure
®
Integrated Microprocessor User’s Manual, Rev. 3
2-2. User mode programs are restricted to user and MAC
Freescale Semiconductor
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