MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 131

MCF5272VF66

Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet

Specifications of MCF5272VF66

Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant

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5.4.6
The PC breakpoint register (PBR) defines an instruction address for use as part of the trigger. This
register’s contents are compared with the processor’s program counter register when TDR is configured
appropriately. PBR bits are masked by setting corresponding PBMR bits. Results are compared with the
processor’s program counter register, as defined in TDR.
Table 5-12
Figure 5-9
Table 5-13
Freescale Semiconductor
31–0
31–0
Bits
Bits
DRc[4–0]
DRc[4–0]
Reset
Address
Field
Name
R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through
Reset
Mask
Name
Field
R/W
shows PBMR.
describes PBR fields.
describes PBMR fields.
Program Counter Breakpoint/Mask Registers
the BDM port using the
Set
(PBR, PBMR)
31
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the
appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
31
Descriptions.”
PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint trigger.
Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG
Figure 5-10. Program Counter Breakpoint Mask Register (PBMR)
MCF5272 ColdFire
Figure 5-9. Program Counter Breakpoint Register (PBR)
instruction and via the BDM port using the wdmreg command.
RDMREG
Table 5-13. PBMR Field Descriptions
Table 5-12. PBR Field Descriptions
®
and
Integrated Microprocessor User’s Manual, Rev. 3
WDMREG
Program Counter
commands using values shown in
Description
0x08
Mask
0x09
Description
Figure 5-9
shows the PC breakpoint register.
Section 5.5.3.3, “Command
Debug Support
0
0
5-13

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