MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 312

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Physical Layer Interface Controller (PLIC)
13.5.2
All bits in these registers are read only and are set on hardware or software reset.
The PnB2RR registers contain the last four frames of data received on channel B2. (P0B2RR is the B2
channel data for port 0, P1B2RR is B2 for port 1, and so on.) The data are packed from LSB to MSB.
These registers are aligned on long-word boundaries from MBAR + 0x310 for P0B2RR to
MBAR + 0x31C for P3B2RR. See
frame and bit alignment within the 32-bit word.
Figure 13-14
13.5.3
All bits in these registers are read-only and are set on hardware or software reset.
The PnDRR registers contain the last four frames of D-channel receive data packed from the least
significant bit, (lsb), to the most significant bit, (msb), for each of the four physical ports on the MCF5272.
P0DRR is the D-channel byte for port 0, P1DRR the D channel for port 1, and so on.
Each of the four byte-addressable registers, P0DRR-P3DRR, are packed to form one 32-bit register,
PnDRR, located at MBAR + 0x320. P0DRR is located in the MSB of the PnDRR register, P3DRR is
located in the LSB of the PnDRR register.
13-16
Reset
Reset
Reset
Reset
Field
Field
Field
Field
Addr
Addr
R/W
R/W
R/W
R/W
B2 Data Receive Registers (P0B2RR–P3B2RR)
31
15
D Data Receive Registers (P0DRR–P3DRR)
31
15
shows the B2 receive data registers.
MBAR + 0x310 (P0B2RR); 0x314 (P1B2RR); 0x318 (P2B2RR); 0x31C (P3B2RR)
MCF5272 ColdFire
Figure 13-14. B2 Receive Data Registers P0B2RR – P3B2RR
MBAR + 0x320 (P0DRR); 0x321 (P1DRR); 0x322 (P2DRR); 0x323 (P3DRR)
Figure 13-15. D Receive Data Registers P0DRR–P3DRR
1111_1111
1111_1111
1111_1111
1111_1111
Frame 0
Frame 2
P0DRR
P2DRR
Section 13.2.3, “GCI/IDL B- and D-Channel Bit
®
Integrated Microprocessor User’s Manual, Rev. 3
Read Only
Read Only
Read Only
Read Only
24
24
8
8
23
23
7
7
1111_1111
1111_1111
1111_1111
1111_1111
Frame 1
Frame 3
P1DRR
P3DRR
Freescale Semiconductor
Alignment,” for the
16
16
0
0