MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 335
MCF5272VF66
Manufacturer Part Number
MCF5272VF66
Description
Manufacturer
Freescale
Datasheet
1.MCF5272VF66.pdf
(544 pages)
Specifications of MCF5272VF66
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Not Compliant
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delay 2. Programmable delay 2 generates a delayed frame sync with reference to FSC1. Similarly
CODECs 5 and 6 are connected to DFSC3 which is the output of programmable delay 3. Programmable
delay 3 generates a delayed frame sync also with reference to FSC1. The MC14LC5480 CODECs, when
in IDL mode, may be programmed using the FSR pin, to select whether the CODEC is receiving and
transmitting on the B1 or the B2 time slot. See the MC14LC5480 data sheet for further information.
Figure 13-38
standard IDL2 10-bit mode with a common frame sync.
The S/T transceiver is connected to port 0, Din0/Dout0. The DCL and FSC generated from the S/T
transceiver are connected to DCL0, FSC0, and also feed port 1, DCL1, and FSC1 because port 1 is
synchronized to these S/T generated timing signals. The six CODECs are connected to Din1 and Dout1.
To provide six discrete 64-Kbps channels on the port 1 IDL interface, the delayed frame syncs are
programmed to synchronize the CODECs on non-overlapping time slots. CODEC 1 transmits and receives
in the B1 time slot. CODEC 2 transmits and receives in the B2 time slot, which starts 10 DCL cycles later,
and so on for the other CODECs. CODECs 3 and 4 are synchronized to DFSC2 which is generated 20 DCL
cycles after FSC1 by loading the programmable delay 2 register with 0x0014. The DFSC3 signal
synchronizes CODECs 5 and 6. DFSC3 is generated 40 DCL cycles after FSC1 by loading the
programmable delay 3 register with 0x0028.
Only the port 0 D-channel is used in this example; DREQ0 and DGNT0 are connected to the S/T
transceiver.
The GCI mode of operation is analogous. In GCI mode, port 0 can be configured to support the SCIT
channel.
Freescale Semiconductor
FSC0
FSC1
DFSC2
Din0/
Dout0
DFSC3
Din1/
Dout1
DCL
shows the IDL bus timing relationship of the CODECs and MC145574 transceiver when in
CODEC 1
B1
B1
MC145574
MCF5272 ColdFire
D
CODEC 2
Figure 13-38. Standard IDL2 10-Bit Mode
B2
B2
®
Integrated Microprocessor User’s Manual, Rev. 3
D
CODEC 3
B3
CODEC 4
B4
Physical Layer Interface Controller (PLIC)
CODEC5
B5
CODEC6
B6
13-39
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