MCF5272VF66 Freescale, MCF5272VF66 Datasheet - Page 472

• Manufacturer Part Number: MCF5272VF66
• Manufacturer: Freescale

Specifications of MCF5272VF66

• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Bus Operation
A normal reset causes all bus activity except SDRAM refresh cycles to terminate. During a normal reset,
SDRAM refresh cycles continue to occur at the programmed rate and with the programmed waveform
timing. In addition, normal reset initializes registers appropriately for a reset exception. During a normal
reset, SCR[RSTSRC] is set to 0b01 to indicate assertion of RSTI with DRESETEN negated caused the
previous reset.
20.12.3 Software Watchdog Timer Reset Operation
A software watchdog timer is provided to allow periodic monitoring of software activity. If the software
watchdog is not periodically accessed by software it can programmed to generate a reset after a timeout
period. When the timeout occurs, an internal reset is asserted for 32K clocks, resetting internal registers as
with a normal reset. The RSTO pin simultaneously asserts for 32K clocks after the software watchdog
timeout.
During the software watchdog timer reset period, all outputs are driven to their default levels. Once RSTO
negates, all bus signals continue to remain in this state until the ColdFire core begins the first bus cycle for
reset exception processing.
During a software watchdog timer reset, SCE[RSTSRC] is set to 0b10 to indicate the software watchdog
as the source of the previous reset.
20-24
CLKIN
SOFTWARE
WATCHDOG
TIMEOUT
INTERNAL
RSTI
RSTO
BUS SIGNALS
Figure 20-23
Like the normal reset, the internal reset generated by a software watchdog
timeout does not reset the SDRAM controller unless DRESETEN is low
during the reset. When DRESETEN is high, SDRAM refreshes continue to
be generated during and after the reset at the programmed rate and with the
programmed waveform timing.
MCF5272 ColdFire
illustrates the timing of RSTO when asserted by a software watchdog timeout.
Figure 20-23. Software Watchdog Timer Reset Timing
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
CLKIN CYCLES
T = 32K
Freescale Semiconductor