AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 11

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
List of Figures
Figure 73. BOFF# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 74. Basic Locked Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 75. Locked Operation with BOFF# Intervention. . . . . . . . . . . . . . 187
Figure 76. Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . . . . 189
Figure 77. Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . . . . . . . 191
Figure 78. Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 79. Stop Grant and Stop Clock Modes, Part 1 . . . . . . . . . . . . . . . . 194
Figure 80. Stop Grant and Stop Clock Modes, Part 2 . . . . . . . . . . . . . . . . 195
Figure 81. INIT-Initiated Transition from Protected Mode to Real
Figure 82. L1 and L2 Cache Organization for the AMD-K6™-IIIE+
Figure 83. L1 Cache Sector Organization. . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 84. Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 217
Figure 85. Write Allocate Logic Mechanisms and Conditions . . . . . . . . . 218
Figure 86. Page Flush/Invalidate Register (PFIR) . . . . . . . . . . . . . . . . . . 224
Figure 87. UC/WC Cacheability Control Register (UWCCR) . . . . . . . . . 232
Figure 88. External Logic for Supporting Floating-Point Exceptions. . . 239
Figure 89. SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 90. TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 91. L2 Cache Organization for AMD-K6™-IIIE+ Processor . . . . . 265
Figure 92. L2 Cache Sector and Line Organization . . . . . . . . . . . . . . . . . 265
Figure 93. L2 Tag or Data Location for the AMD-K6™-IIIE+
Figure 94. L2 Data - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 95. L2 Tag Information for the AMD-K6™-IIIE+
Figure 96. LRU Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 97. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 98. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 99. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 100. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 272
Figure 101. Clock Control State Transitions for Standard-Power
Figure 102. Clock Control State Transitions for Low-Power
Figure 103. Suggested Component Placement for CPGA Package . . . . . . 294
Figure 104. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 105. Key to Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Processor—EDX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Processor—EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Versions of the AMD-K6™-IIIE+ Processor . . . . . . . . . . . . . . . 278
Versions of the AMD-K6™-IIIE+ Processor . . . . . . . . . . . . . . . 279
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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