AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 148

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.39
Pin Attribute
Summary
Driven and Floated
126
PWT (Page Writethrough)
Output
The processor drives PWT to indicate the operating system’s
specification of the writeback state or writethrough state for
the page being addressed. PWT, together with WB/WT#,
specifies the data cache-line state during cacheable read misses
and write hits to shared cache lines. See “WB/WT# (Writeback
or Writethrough)” on page 139 for more details.
The state of PWT depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
PWT is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
PWT is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD.
In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CR0 set to 0):
In Protected and Virtual-8086 modes while paging is
enabled (PG bit in CR0 set to 1):
•
•
•
PWT output = 0 (writeback state)
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PWT output = PWT bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PWT output = PWT bit in page directory entry
For accesses to 4-Kbyte pages:
PWT output = PWT bit in page table entry
Preliminary Information
Signal Descriptions
23543A/0—September 2000
Chapter 5