AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 239

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Figure 84. Write Handling Control Register (WHCR)
Chapter 9
Symbol
Notes: Hardware RESET initializes this MSR to all zeros.
63
WAELIM
WAE15M
Description
Write Allocate Enable Limit
Write Allocate Enable 15-to-16-Mbyte 16
Reserved
Write Allocate Enable Limit Field. The WAELIM field is 10 bits wide.
This field, multiplied by 4 Mbytes, defines an upper memory
limit. Any pending write cycle that misses the L1 cache and that
addresses memory below this limit causes the processor to
perform a write allocate (assuming the address is not within a
range where write allocates are disallowed). Write allocate is
disabled for memory accesses at and above this limit unless the
processor determines a pending write cycle is cacheable by
means of one of the other write allocate mechanisms—“Write
to a Cacheable Page” and “Write to a Sector.” The maximum
value of this limit is ((2
all the bits in this field are set to 0, all memory is above this
limit and write allocates due to this mechanism is disabled
(even if all bits in the WAELIM field are set to 0, write allocates
can still occur due to the “Write to a Cacheable Page” and
“Write to a Sector” mechanisms).
Write Allocate Enable 15-to-16-Mbyte Bit. The Write Allocate Enable
1 5-t o -1 6 -M by t e ( WA E1 5 M) b it i s u se d t o e n able w r it e
allocations for memory write cycles that address the 1 Mbyte of
memory between 15 Mbytes and 16 Mbytes. This bit must be set
to 1 to allow write allocate in this memory area. This bit is
provided t o account for a small number of uncommon
memory-mapped I/O adapters that use this particular memory
address space. If the system contains one of these peripherals,
the bit should be set to 0 (even if the WAE15M bit is set to 0,
write allocates can still occur between 15 Mbytes and 16
Mbytes due to the “Write to a Cacheable Page” and “Write to a
31-22
Bits
Cache Organization
32
31
WAELIM
10
AMD-K6™-IIIE+ Embedded Processor Data Sheet
–1) · 4 Mbytes) = 4092 Mbytes. When
22
21
17
16
W
M
A
E
1
5
15
0
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