AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 329
AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
Lead Free Status / RoHS Status
Not Compliant
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23543A/0—September 2000
Table 67. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and hold
Chapter 16
Symbol
times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must remain
asserted at least two clocks.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
73
74
75
82
83
84
85
86
87
76
77
78
79
80
81
88
89
2
1
1
2
2
2
2
1
1
Parameter Description
INIT Hold Time
INTR Setup Time
INTR Hold Time
INV Setup Time
INV Hold Time
KEN# Setup Time
KEN# Hold Time
NA# Setup Time
NA# Hold Time
NMI Setup Time
NMI Hold Time
SMI# Setup Time
SMI# Hold Time
STPCLK# Setup Time
STPCLK# Hold Time
WB/WT# Setup Time
WB/WT# Hold Time
Signal Switching Characteristics
AMD-K6™-IIIE+ Embedded Processor Data Sheet
5.0 ns
5.0 ns
5.0 ns
4.5 ns
5.0 ns
5.0 ns
5.0 ns
4.5 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
Min
Preliminary Data
Max
Figure
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