AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 245

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Internal Snooping
FLUSH#
Page Flush/Invalidate
Register (PFIR)
Chapter 9
Internal snooping is initiated by the processor (rather than
system logic) during certain cache accesses. It is used to
maintain coherency between the L1 instruction cache and the
L1 data cache.
The processor automatically snoops its L1 instruction cache
during read or write misses to its L1 data cache, and it snoops
its L1 data cache during read misses to its L1 instruction cache.
The L2 cache is not snooped during misses to either of the L1
caches. Table 41 on page 226 summarizes the actions taken
during this internal snooping.
If an internal snoop hits its target, the processor does the
following:
In response to sampling FLUSH# asserted, the processor writes
back any L1 data cache lines and L2 cache lines that are in the
modified state and then marks all lines in the L1 instruction
cache, the L1 data cache, and the L2 cache as invalid.
T h e A M D -K 6 -I I I E + p r o c e s s o r c o n t a i n s t h e Pa g e
Flush/Invalidate Register (PFIR) that allows cache invalidation
and optional flushing of a specific 4-Kbyte page from the linear
address space (see Figure 86 on page 224). When the PFIR is
written to (using the WRMSR instruction), the invalidation
and, optionally, the flushing begins. The total amount of cache
in the AMD-K6-IIIE+ processor is 320 Kbytes. Using this
register can result in a much lower cycle count for flushing
particular pages versus flushing the entire cache.
L1 Data Cache Snoop During an L1 Instruction-cache Read
Miss—If modified, the line in the L1 data cache is written
back. If the writeback hits the L2 cache, the cache line is
stored in the L2 cache in the modified state and no
writeback occurs on the system bus. If the writeback misses
the L2 cache, the cache line is written back on the system
bus to external memory. Regardless of its state, the L1
data-cache line is invalidated and the L1 instruction cache
performs a read from either the L2 cache (if a L2 hit occurs)
or external memory (if a L2 miss occurs).
L1 Instruction Cache Snoop During an L1 Data Cache
Miss—The line in the instruction cache is marked invalid,
and the L1 data-cache read or write is performed as defined
in Table 39 on page 221.
Cache Organization
AMD-K6™-IIIE+ Embedded Processor Data Sheet
223