AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 231

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Chapter 9
The operating system can control the cacheability of a page.
The paging mechanism is controlled by CR3, the Page Directory
Entry (PDE), and the Page Table Entry (PTE). Within CR3,
PDE, and PTE are Page Cache Disable (PCD) and Page
Writethrough (PWT) bits. The values of the PCD and PWT bits
used in Table 36 on page 210 and Table 37 on page 210 are
taken from either the PTE or PDE. For more information on
PCD and PWT, see “PCD (Page Cache Disable)” on page 124
and “PWT (Page Writethrough)” on page 126, respectively.
The AMD-K6-IIIE+ processor does not enforce any rules of
inclusion or exclusion as part of the protocol defined for the
L1 and L2 caches. However, there are certain restrictions
imposed by design on the allowable MESI states of a cache
line that exists in both the L1 cache and the L2 cache. Refer
to Table 40 on page 225 for a list of the valid cache-line
states allowed.
When CD is set to 0 and NW is set to 1, an invalid mode of
operation exists that causes a general protection fault to
occur.
When CD is set to 1 (disabled) and NW is set to 0, the cache
fill mechanism is disabled but the contents of the cache are
still valid. The processor reads from the caches if the read
hits the L1 or the L2 cache. If a read misses both the L1 and
the L2 caches, a line fill does not occur on the system bus.
Write hits to the L1 or L2 cache are updated, while write
misses and writes to shared lines cause external memory
updates. If PWT is driven Low and WB/WT# is sampled
High, a write hit to a shared line changes the cache-line state
to exclusive.
When the CD and NW bits are both set to 1, the cache is fully
disabled. Even though the cache is disabled, the contents
are not necessarily invalid. The processor reads from the
caches if the read hits the L1 or the L2 cache. If a read
misses both the L1 and the L2 caches, a line fill does not
occur on the system bus. If a write hits the L1 or the L2
cache, the cache is updated but an external memory update
does not occur. If a cache line is in the exclusive state during
a write hit, the cache-line state is changed to modified.
Cache lines in the shared state remain in the shared state
after a write hit. Write misses access external memory
directly.
Cache Organization
AMD-K6™-IIIE+ Embedded Processor Data Sheet
209