AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 275

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
13.3
Test Access Port
Chapter 13
Boundary-Scan Test Access Port (TAP)
The Three-State Test mode is exited when the processor
samples RESET asserted.
The boundary-scan Test Access Port (TAP) is an IEEE standard
that defines synchronous scanning test methods for complex
logic circuits, such as boards containing a processor. The
AMD-K6-IIIE+ processor supports the TAP standard defined in
the I EEE Standard Test Acces s Port and Bo undary-Scan
Architecture (IEEE 1149.1-1990) specification.
Boundary scan testing uses a shift register consisting of the
serial interconnection of boundary-scan cells that correspond to
each I/O buffer of the processor. This non-inverting register
chain, called a Boundary Scan Register (BSR), can be used to
capture the state of every processor pin and to drive every
processor output and bidirectional pin to a known state.
Each BSR of every component on a board that implements the
boundary-scan architecture can be serially interconnected to
enable component interconnect testing.
The TAP consists of the following:
TDO is never floated because the Boundary-Scan Test
Access Port must remain enabled at all times, including
during the Three-State Test mode.
Test Access Port (TAP) Controller—The TAP controller is a
synchronous, finite state machine that uses the TMS and
TDI input signals to control a sequence of test operations.
See “TAP Controller State Machine” on page 260 for a list of
TAP states and their definition.
Instruction Register (IR)—The IR contains the instructions
that select the test operation to be performed and the Test
Data Register (TDR) to be selected. See “TAP Registers” on
page 255 for more details on the IR.
Test Data Registers (TDR)—The three TDRs are used to
process the test data. Each TDR is selected by an instruction
in the Instruction Register (IR). See “TAP Registers” on
page 255 for a list of these registers and their functions.
Test and Debug
AMD-K6™-IIIE+ Embedded Processor Data Sheet
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