AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 230

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
9.2
9.3
208
Predecode Bits
Cache Operation
Decoding x86 instructions is particularly difficult because the
instructions vary in length, ranging from 1 to 15 bytes long.
Predecode logic supplies the predecode bits associated with
each instruction byte.
Predecode bits indicate the number of bytes to the start of the
next x86 instruction. The predecode bits are passed with the
instruction bytes to the decoders where they assist with parallel
x86 instruction decoding. The predecode bits use memory
separate from the 32-K byte L1 instruc tion c ache. The
predecode bits are stored in an extended L1 instruction cache
alongside each x86 instruction byte as shown in Figure 83 on
page 207.
The L2 cache does not store predecode bits. As an instruction
cache line is fetched from the L2 cache, the predecode bits are
generated and stored alongside the cache line in the L1
instruction cache in the same manner as if the cache line were
fetched from the processor’s system bus.
The operating modes for the caches are configured by software
using the not writethrough (NW) and cache disable (CD) bits of
control register 0 (CR0 bits 29 and 30, respectively). These bits
are used in all operating modes.
Note: A write allocate operation can modify the behavior of write
When the CD and NW bits are both set to 0, the cache is fully
enabled. This is the standard operating mode for the cache.
If a L1 cache read miss occurs, the processor determines if
the read hits the L2 cache, in which case the cache line is
supplied from the L2 cache to the L1 cache. If a read misses
both the L1 and the L2 caches, a line fill (32-byte burst read)
on the system bus occurs in order to fetch the cache line. The
cache line is then filled in both the L1 and the L2 caches.
Write hits to the L1 and L2 caches are updated, while write
misses and writes to shared lines cause external memory
updates. Refer to Table 39 on page 221 for a summary of
cache read and write cycles and the effect of these
operations on the cache MESI state.
misses to the caches. See “Write Allocate” on page 215.
Preliminary Information
Cache Organization
23543A/0—September 2000
Chapter 9