AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 131
AMD-K6-IIIE+550ACR
Manufacturer Part Number
AMD-K6-IIIE+550ACR
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.AMD-K6-IIIE550ACR.pdf
(370 pages)
Specifications of AMD-K6-IIIE+550ACR
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23543A/0—September 2000
5.20
Pin Attribute
Summary
Sampled
Chapter 5
EADS# (External Address Strobe)
The processor always floats DP[7:0] except when they are being
driven during a write cycle as described above. In addition,
DP[7:0] are floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts
HLDA in recognition of HOLD.
Input
System logic asserts EADS # during a cache inquire cycle to
indicate that the address bus contains a valid address. EADS#
can only be driven after the system logic has taken control of
the address bus by asserting AHOLD or BOFF# or by receiving
HLDA. The processor responds to the sampling of EADS# and
the address bus by driving HIT#, which indicates if the inquired
cache line exists in the processor’s caches, and HITM #, which
indicates if it is in the modified state.
If AHOLD or BOFF# is asserted by the system logic in order to
execute a cache inquire cycle, the processor begins sampling
EADS # two clock edges after AHOLD or BOFF # is sampled
asserted. If the system logic asserts HOLD in order to execute a
cache inquire cycle, the processor begins sampling EADS# two
clock edges after the clock edge HLDA is asserted by the
processor.
EADS# is ignored during the following conditions:
One clock edge after the clock edge on which EADS# is
sampled asserted
Two clock edges after the clock edge on which ADS# is
asserted
When the processor is driving the address bus
When the processor asserts HITM#
Signal Descriptions
AMD-K6™-IIIE+ Embedded Processor Data Sheet
109
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