AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 302

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

AMD-K6™-IIIE+ Embedded Processor Data Sheet
14.2
Enter Halt State
Exit Halt State
14.3
Enter Stop Grant
State
280
Halt State
Stop Grant State
During the execution of the HLT instruction, the AMD-K6-IIIE+
processor executes a Halt special cycle. After BRDY# is
sampled asserted during this cycle, and then EWBE# is also
sampled asserted (if not masked off), the processor enters the
Halt state in which the processor disables most of its internal
clock distribution. In order to support the following operations,
the internal phase-lock loop (PLL) still runs, and some internal
resources are still clocked in the Halt state:
After entering the Halt state, all signals driven by the processor
retain their state as they existed following the completion of
the Halt special cycle.
The AMD-K6-IIIE+ processor remains in the Halt state until it
samples INIT, INTR (if interrupts are enabled), NMI, RESET, or
SMI# asserted. If any of these signals is sampled asserted, the
processor returns to the Normal state and performs the
corresponding operation. All of the normal requirements for
recognition of these input signals apply within the Halt state.
After recognizing the assertion of STPCLK#, the AMD-K6-IIIE+
processor flushes its instruction pipelines, completes all
pending and in-progress bus cycles, and acknowledges the
Inquire Cycles—The processor continues to sample AHOLD,
BOFF#, and HOLD in order to support inquire cycles that
are initiated by the system logic. The processor transitions to
the Stop Grant Inquire state during the inquire cycle. After
returning to the Halt state following the inquire cycle, the
processor does not execute another Halt special cycle.
Flush Cycles—The processor continues to sample FLUSH#.
If FLUSH# is sampled asserted, the processor performs the
flush operation in the same manner as it is performed in the
Normal state. Upon completing the flush operation, the
processor executes the Halt special cycle, which indicates
the processor is in the Halt state.
Time Stamp Counter (TSC)—The TSC continues to count in
the Halt state.
Signal Sampling—The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
Preliminary Information
Clock Control
23543A/0—September 2000
Chapter 14